When the programmable logic controller is put into operation, its working process is generally divided into three stages: input sampling, user program execution, and output refreshing. Completing these three stages is called one scan cycle. During the entire operation period, the CPU of the programmable logic controller repeats the execution of these three stages at a certain scanning speed. [5]
Input Sampling
During the input sampling stage, the programmable logic controller reads in all input states and data sequentially in a scanning manner and stores them in the corresponding units in the I/O image area. After the input sampling is completed, it proceeds to the user program execution and output refresh stage. During these two stages, even if the input states and data change, the states and data in the corresponding units of the I/O image area will not change. Therefore, if the input is a pulse signal, the width of this pulse signal must be greater than one scan cycle to ensure that the input can be read in under any circumstances. [5]
User program execution
During the execution of the user program, the programmable logic controller always scans the user program (ladder diagram) in a top-down sequence. When scanning each ladder diagram, it always first scans the control circuit composed of the contacts on the left side of the ladder diagram, and performs logical operations on the control circuit composed of the contacts in the order of left to right and top to bottom. Then, based on the result of the logical operation, it refreshes the state of the corresponding bit of the logic coil in the system RAM storage area; or refreshes the state of the corresponding bit of the output coil in the I/O image area; or determines whether to execute the special function instruction specified by the ladder diagram. [5]
That is, during the execution of the user program, only the states and data of the input points within the I/O image area will not change, while the states and data of other output points and software devices within the I/O image area or the system RAM storage area may change. Moreover, the program execution result of the top-level ladder diagram will affect all the ladder diagrams below that use these coils or data; conversely, the status or data of the refreshed logic coils in the lower-level ladder diagram can only take effect on the program above it in the next scanning cycle. [5]
During the execution of the program, if the immediate I/O instruction is used, the I/O points can be accessed directly. That is, if the I/O instruction is used, the value of the input process image register will not be updated. The program directly fetches the value from the I/O module, and the output process image register will be updated immediately. This is somewhat different from immediate input. [5]
Output Refresh
After the user program is scanned, the programmable logic controller enters the output refresh stage. During this period, the CPU refreshes all the output latch circuits according to the corresponding states and data in the I/O mapping area, and then drives the corresponding peripheral devices through the output circuit. This is the actual output of the programmable logic controller. [5]
Summary
Based on the description of the above process, the characteristics of the PLC working process can be summarized as follows: [7]
① The PLC adopts a centralized sampling and centralized output working mode, which reduces the influence of external interference. [5]
② The working process of PLC is a cyclic scanning process. The length of the scanning cycle depends on factors such as the execution speed of instructions and the length of the user program. [5]
③ The influence of output on input shows a lag phenomenon. The PLC adopts a centralized sampling and centralized output working mode. After the sampling stage is completed, the change in input status will not be received until the next sampling cycle. Therefore, the length of this lag time mainly depends on the length of the cycle. In addition, factors affecting the lag time also include the input filtering time and the lag time of the output circuit, etc. [5]
The content of the output image register depends on the result of the user program’s scanning execution. [5]
The content of the output latch is determined by the data in the output image register during the previous output refresh period. [5]
The current actual output status of the PLC is determined by the content of the output latch.